EMULATION TOOL FOR TESTING FAULT TOLERANCE

Abstract

The aim of this paper is to show a possible adaptation of the well known microprocessor emulation method for testing fault tolerance, and to examine the advantages of the adap-tation. First a survey on test methods and their application will be given with respect to the possibilities for testing fault tolerant architectures. It will be followed by a short overview of different microprocessor fault models, and the fault injection routines based on the fault models. The injection routines require some hardware extension of the con-ventional microprocessor in-circuit emulator. The necessary extensions are shown on a MC68000 based in-circuit emulator. Finally, some improvement possibilities are discussed.